A20-SOM: GPIO Extension Headers

[bruceuk]

Hi

I've been looking at the A20-SOM schematic:
https://www.olimex.com/Products/SOM/A20/A20-SOM/resources/A20-SOM_schematic.pdf

And I'm struggling to find:
SPI0
SPI3
I2C
SDIO (want to attach a wifi module)

Anybody familiar with the headers and could shed some light?


Thanks
Bruce

[dave-at-axon]

A lot of the A20 pins are multiplexed so may not be available if their alternative functions is being used but you might be in luck with what you are looking for.

SPI0 is on CPU pins M22 and M23 but used to control the NAND flash. The alternative is on C16, D16 and D17 and C17 (PH10, 11, 12 and 13) You'll find them split across GPIO3 and 4. GPIO4 has them as UART6.

I2C is available on GPIO4 as TWI2 pins 29 and 30. There is also TWI1 on pins 21 and 22.

SDIO3 would appear to be on GPIO5 (at least as a standard SD card interface but it should work) The onboard MicroSD uses the SDIO0 port.

You'll need to ensure that any boot configuration adopts the mode you need. I am not familiar with the A20-SOM, only the A20 board itself and it uses the FEX file to configure the pins.

Hope this helps?

[bruceuk]

Hi Dave

That is most helpful, thank you!

How are you able to map "header pins" to "cpu pins" ? I understand cpu pin function needs to be toggled (via dts or flex) to enable a desired function.....but I've been struggling to see which GPIO pin maps to which processor pin.


The schematic offered here:
https://www.olimex.com/Products/SOM/A20/A20-SOM/resources/A20-SOM_schematic.pdf

Doesn't offer that sort of detail.

Fantastic little board this A20-SOM .... guess all new things come with a learning curve

[jmyreen]

bruceuk, you will have to match the GPIO connector signals names with the signal names on the processor. For example, UART7-RX is connected to processor pin E13 and GPIO-4 pin 20. Note that not all processor I/O pins are available on the GPIO connectors.

[dave-at-axon]

@Bbuceuk.

Grab the A20 datasheet from the Olimex wiki and you will find all of the multiplex capability for each pin.

On the A20 Android build there is a FEX file that is used to configure the pins. Study this and you should be able to work out what each one does. This link also helps.

http://linux-sunxi.org/Fex_Guide

[pankajmisra]

For fex guide visit
http://linux-sunxi.org/Fex_Guide

check "Port Definitions". It explains 5 parameters you pass along with pin number.

port:<port><mux feature><pullup/down><drive capability><output level>

A20 programmable pins & their MUX-feature values are given here... http://linux-sunxi.org/A20/PIO