SWD Failure when Radio out of Reset

[nmap]

Hi All,

  This is a long shot, but if anyone could help with this issue I would be most grateful.

  I'm using an STM32F103 with a Digi XBee-900HP mesh radio module. I debug from an Olimex ARM-USB-TINY-H using OpenOCD/gdb on Linux.

  If I hold the XBee radio in reset (RST=Low), SWD works fine. As soon as I bring the radio out of reset (RST=High), I get an SWD error in gdb:

Code Select Expand


Invalid ACK 0x7 in JTAG-DP transaction
Polling target stm32f1x.cpu failed, GDB will be halted. Polling again in 100ms
[Remote target] #1 stopped.

  Then the debugger doesn't work at all (not even to reflash) until I put the radio back in reset. Amazingly, when the radio is in reset again, SWD starts working again:

Code Select Expand

WARNING! The target is already running. All changes GDB did to registers will be discarded! Waiting for target to halt.

^C
Program received signal SIGINT, Interrupt.
0x08021688 in _idle_thread (p=0x0) at ../libraries/<filename removed>:57
57        <function name removed>
(gdb)

Some other info:

• Power supply is stable at 3.3V the whole time.
• TDO line on SWD port raises only to 2.5V, but an extra 10K pullup to 3.3V does not fix the issue.
• arm-none-eabi-gdb version: 7.6.50.20131218-0ubuntu1+1 7.6.50.20131218-cvs
• Open On-Chip Debugger 0.7.0 (2013-10-22-08:31)

Any tips?

Thanks,
Chris

[JohnS]

I'd check how they're wired together, then suspect noise - crosstalk, EMI, etc.

Have you a 'scope to look at signals?  DSO from choice.

Might be able to run at lower clock?  I know JTAG can but don't know SWD that well.

Maybe try some bypass caps.

John

[nmap]

Thanks for the reply, John.

You were right that I needed to check my wiring. I found the cause of the problem and fixed it.

The CTS line from the XBee is wired to PB4 on the STM32F1, which also has the function of NJTRST.
So, when the XBee came out of reset, it pulled down the CTS line (saying "I'm ready to accept bytes over serial."), and this caused the STM32 to reset the JTAG/SWD module.

I suppose I could move to another pin, but there are not many free pins in this design. So, I just set SWJ_CFG[2:0] to 0b001 which disables the NJTRST function but keeps full SWD functionality:

Code Select Expand

/* Disable NJTRST */
AFIO->MAPR = (AFIO->MAPR & ~AFIO_MAPR_SWJ_CFG) | AFIO_MAPR_SWJ_CFG_NOJNTRST;


(This is ChibiOS 2.6 register defines.)

I placed this code early in my main(), however there is still a remote possibility that the debugger would have trouble prior to that line. So I don't recommend others to use the TRST pin for GPIO!

[JohnS]

Wow, well done figuring it out so fast!

John