openocd jtag a20-olinuxino-micro-4gb

[vision]

Hi there,

can anyone tell me how to setup a development environment with jtag debugging, openocd, arm-usb-tiny-h and a20-olinuxino-micro-4gb board. Bought this tools to learn something about kernel, and driver development. I have already an Eclipse IDE with a proper toolchain working. Now i want to debug with jtag interface. I found nothing to configure openocd and to connect jtag pins. Please tell me, whether this is possible, or not. Maybe i search myself to death.

Thank you.

[deskwizard]

If you look at the fex and the kernel pack script, you will see an option for debug on sdcard slot.
I'd look at the board schematic and see if those pins correspond to the a20 jtag

Going from memory here so no guarantee.

Let us know what you find out!

Dw

[JohnS]

Presumably you already asked on openocd ML and linux-sunxi ML.

I don't think there are pre-existing scripts, though I didn't need any so could have missed them.

Maybe the datasheets tell you enough to write them if they don't exist - it's ARM...

John

[Christophe]

Hello,

I have working on this context (openocd , A20-olinuxino-micro-4gb and Arm-usb-tiny-h) for four days. Until today, I could not stop the processor to enter in the "halting debug-mode" (the "halt" command in openocd failed => timeout). As the processor must be in the "halting debug-mode" to use a lot of openocd commands, it was impossible to do interesting things.

But thanks to you, now it works. In fact, as I want to give you information about my work, I simplified my target script for openocd and this action suppressed a bug  (now I can enter in the "halting debug-mode" state of the processor)
      - Of course, as it works only for five minutes I have not used all the possibilities of openocd. I tried the commands :
          o "arm reg" => the answer is "Microcontroller Profile not supported – use standard reg cmd"
          o "reg" : it works,
          o "arm disassemble" : it works
          o "halt" : it works (to  halt a processor)
          o "resume" : it works (to resume the execution on an halted processor)
          o At this time I have to complete scripts used by openocd (taget and board) because commands like "reset" returns "how to reset ?"

Hereafter my environment:
      - A20-olinuxino-micro-4gb
      - Arm-usb-tiny-h (Olimex)
      - Openocd 0.9 and 0.10-dev
      - I don't use u-boot nor Linux
      - I wrote a test program (assembly and C code) loaded at the boot time. This program initialize the two cores and, with a menu, allows me to display and modify the contents of the memory and ARM coprocessor CP15 and CP14.
      - Gcc-linaro-4.9-2015.0-3-x86_64_arm-linux-gnueabihf

Arm-usb-tiny-h (Olimex)
      - the pinout of this device is given at https://www.olimex.com/Products/ARM/JTAG/_resources/openocd-jtag-layout.png
      - An other interesting file : http://www2.lauterbach.com/pdf/arm_app_jtag.pdf. In this file you could notice that TDO (Test Data Output) is an INPUT from the point of view of the connector => You must connect this pin to the TDO pin on the A20-olinuxino-micro-4gb (of course the same reasoning applies to TDI)
      - To know the pin number and the GPIO connector to use on your board, have a look at https://www.olimex.com/Products/OLinuXino/A20/A20-OLinuXino-MICRO-4GB/resources/A20-OLinuXino-Micro.pdf
          o The connector, where these pins are located, is GPIO-3
          o In this manual, you have also the schema of the connector. This will allow you to identify the position of each pin (1 to 40)
          o If you want to use the RESET_N signal, DON'T USE the file at http://www.py6zgp.com/download/A20-GPIO.pdf to identify this pin on the GPIO-2 connector (for me, to be conform to the pin out of this kind of connector you have to swap all pin numbers [2 with 40] ; [4 with 38]; [6 with 36]  ...... [18 with 24]; [20 with 22] ; the same kind of swap must be done for the odd number pins (To confirm this, I suggest you to use a multimeter and try to locate +5 V, +3 V and the ground of this connector). For me, I believe the pin numbering of the others connectors is correct (GPIO-1, GPIO-3, LCD_CON).

      - As there is no JTAG connector on the board, you will have to use at least 6 independent wires with a female connector at each end to connect your Arm-usb-tiny-h to your A20-olinuxino-micro-4gb (I unplugged the cable shipped with the Arm-usb-tiny-h adaper)
          o TDI, TDO, TCK, TMS, GND and +3,3 V (I used pin 1 on Arm-usb-tiny-h to receive the +3,3 V reference from the board)

GPIO
      - You have to program the GPIO which is on your board (A20-olinuxino-micro-4gb) in order to redirect the JATG signals (TDI, TDO, TCK, TMS) toward GPIO-3 pins.
          o As I said, I don't use Linux. So I cannot tell you how to configure the GPIO with Linux.
          o In the file http://www.py6zgp.com/download/A20-GPIO.pdf you have a tutorial to configure the GPIO with Linux (may be it will help you in this task). If you use a recent kernel, perhaps the "script.fex" file will not be used and you will have to use a standard tool (not a sunxi tool)
          o In the file https://www.olimex.com/Products/OLinuXino/A20/A20-OLinuXino-MICRO-4GB/resources/A20-OLinuXino-Micro.pdf there are the GPIO ports you have to configure (PB14, PB15, PB16 and PB17)

Openocd
      - The script to use with your debug adapter (Arm-usb-tiny-h) is given with openocd : "olimex-arm-usb-tiny-h.cfg"
      - You have to create your own script for the target. At this time my "target" file contents only the following lines (this configuration allows me to put each processor in the state "halting debug-mode" and allows me to use several commands of openocd):
        adapter_khz 14000
        transport select jtag   
        # the first line beneath is suggested by opendoc (auto probing)
        jtag newtap auto0 tap –irlen 4 –expected-id 0x5ba00477
        target create auto0.cpu0 cortex_a  -chain-position auto0.tap -coreid 0
        target create auto0.cpu1 cortex_a  -chain-position auto0.tap -coreid 1

      o Note :
          > The two cores must be initialized on your board (with u-boot and linux, I think the two cores will be initialized), otherwise you will have a lot of errors (in this case, suppress the line "target create auto0.cpu1 cortex_a  -chain-position auto0.tap -coreid 1").
         

I hope these information will help you to take the right decision (don't forget that at this time the "target" script I gave must be completed. So I cannot affirm you will have the behavior you need).

Christophe

[vision]

Hi Christophe,

much tnx for your reply.

My hardware environment is the same as yours. I would like to see your test program. How do you load this to the target ?
I setup a development environment with eclipse, but can't load a program to the target.

Maybe i need some more board configuration in the openocd scripts.

I'm wondering about the TRST and SRST lines. Are they not necessary ?

I always get this JTAG-DP STICKY ERROR. Do you know something about this ?

Greetings










 

[Christophe]

Hi Vision,

About my test program

     - I load this program the same way as you can load u-boot on the board (I wrote this program on a SD card; I put this SD card in the SD card reader which is on the board, and finally I press and release the reset button on the board. There is no u-boot, or linux, in this SD card, only my own program).


Eclipse

- I do not use Eclipse. So, I cannot help you on this topic, Sorry.


TRST and TSRST

- I don't use the TRST signal, because I don't know if there is a pin on the board to use this signal.

- Sometime I use the TSRST signal, but as I have no skill with electronic circuits I don't know if what I do is correct or hazardous for my board. I connect this signal (the Olimex debug adapter output) to the RESET_N pin on the board (before doing this, I had a look on the electronic schema of the board to be sure there is a pull up on this pin). In this case I use this setup in my script :

                 * reset_config  srst_only  srst_gates_jtag  srst_open_drain
                 * adapter_nsrst_assert_width 1
                 * adapter_nsrst_delay 200

        > 1 (for 1 ms) because I saw in a document that the signal must be at a low level at least 300 µs (I don't test if it possible to give a lower value than 1 ms)
        > 200 (for 200 ms) : my tests show that a value less than 190 (for my board) generates error messages.
        > If I were you, I would forget the use of this signal (unless you know what you are doing). Remember two things : I have no skill with electronic circuits, and my first message about a possible mistake in one of the schemas which identify the RESET_N pin on the board.

     - Most of the time I don't use this signal (SRST) but I don't modify my script. I think that a configuration with only reset_config none would be more appropriated when none of these signals is used.


Questions :

     - Which operating system you use to run Eclipse ? (Windows, Linux, ...)

     - When you power up your A20_Olinux_MICRO_4GB (before you start Eclipse), which program is loaded on this board ?
            * From your first message, I think you use u-boot and linux.  Am I right ?

     - Did you do tests with only openocd (without eclipse) and telnet (just to see if commands like "targets", "halt" and "resume" work, and thus have a status about all the parts of the chain between openocd and the JTAG port on you board processor)  ?
           * Sorry, but with your message, I can't determine if all works fine with Eclipse (except when you want to load a program on your board with Eclipse) or if Eclipse can't globally communicate with your board.


Notes

======================================================================
the script I use :

     adapter_khz 14000
     transport select jtag
     jtag newtap auto0 tap -irlen 4 -expected-id 0x5ba00477
     target create auto0.cpu0 cortex_a -chain-position auto0.tap -coreid 0
     target create auto0.cpu1 cortex_a -chain-position auto0.tap -coreid 1
     reset_config srst_only srst_gates_jtag srst_open_drain
     init
     cortex_a smp_on

The output I obtained with openocd 0.9.0 and telnet (I did not connect the SRST output signal to my board). I used "targets", "halt" and "resume" commands.


chr@aldebaran:~/work/JTAG/openOCD/work$ telnet localhost 4444
Trying ::1...
Trying 127.0.0.1...
Connected to localhost.
Escape character is '^]'.
Open On-Chip Debugger
>
> targets
    TargetName         Type       Endian TapName            State       
--  ------------------ ---------- ------ ------------------ ------------
0  auto0.cpu0         cortex_a   little auto0.tap          running
1* auto0.cpu1         cortex_a   little auto0.tap          running
>
>
> halt
auto0.cpu1 rev 4, partnum c07, arch f, variant 0, implementor 41
auto0.cpu1 cluster 0 core 1 multi core
auto0.cpu1: target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x60000193 pc: 0x00001c64
MMU: disabled, D-Cache: disabled, I-Cache: disabled
>
>
> targets
    TargetName         Type       Endian TapName            State       
--  ------------------ ---------- ------ ------------------ ------------
0  auto0.cpu0         cortex_a   little auto0.tap          running
1* auto0.cpu1         cortex_a   little auto0.tap          halted
>
>
> resume
>
> targets
    TargetName         Type       Endian TapName            State       
--  ------------------ ---------- ------ ------------------ ------------
0  auto0.cpu0         cortex_a   little auto0.tap          running
1* auto0.cpu1         cortex_a   little auto0.tap          running
>

========================================================================================================


Kindly regards
Christophe

[vision]

Hi Christophe,

tnx for reply.

I run Eclipse CDT on the PC with Ubuntu. (build PC). There are plugins for cross development with toolchains and openocd (as gdbserver) support.
Remote debugging with gdbserver on the target, when running Debian jessy, is working fine.

I build the SD card with debian image like described on sunxi. Otherwise i changed nothing on the board. So an installed bootloader should run.

Debugging with JTAG and openocd is not working. Actually i only used openocd with telnet connection.

Always got messages like "Target not halted", "How to reset ?", "Error: JTAG-DP STICKY ERROR
Error: MEM_AP_CSW 0x80000042, MEM_AP_TAR 0x80112080".

My Question is, whether openocd can halt and reset the target without SRST and TRST connection. This should be possible with TMS and TCK, but is this supported by openocd ?

Actually i want to acquire some experience with bootloading and driver development for embedded linux, lowcost version (dont have 10000€ to spare). Maybe i bought the wrong equipment. The capabilities of this board are very good. But less support openocd/JTAG debugging. If possible, i dont want to dive deep in JTAG, FTDI, openocd source code, if someone has a working version for this board.

Kinds regards

[JohnS]

You can ignore Eclipse, gdb, etc for now and just get oocd working,

Christophe looks to have posted enough (or it not then nearly enough) to do that.

Until you can get oocd happy to halt your target and until you can issue commands to oocd you don't need anything like Eclipse/gdb/...  You can put all the commands on the oocd command line for now, no need even to bother with telnet.

I've used oocd with other ARM boards but not yours, but from what has been posted so far it's quite similar.  I've always used SRST etc - see the many sample scripts with oocd.  I'd use them as a guide with what Christophe has very helpfully posted.

John

[vision]

I'm not a hardware geek. But with a magnifying glass, i could connect the TMS, TCK, TDI, TDO lines. So, do u tell me, that connecting "JTAG SRST" to "Board RESET_N" is the solution ?

tnx

[JohnS]

I haven't given it any thought as it's not something I want to do but to work it out I'd read what these are and look at other boards to see what works there.

At some point you just have to put in time and effort

An alternative is to buy a board with a JTAG connector and details of what to do.

John

[Christophe]

Hi Vision,

As shown in the output I gave in my last message, you can see I could halt a core with the "halt" command, and, as I wrote, I did this without SRST and TRST signals (no connection between the Olimex debug adapter and the board).

My PC, where opencd is running, is a PC with Debian/Linux 8.2 (Jessie : 3.16.0-4-amd64).

  - I used two versions of openocd : 0.9.0 and 0.10-dev. Which version are you using ?

  - For these versions, you need  "libusb1.x" . Which version are you using ?

Try also this command (if you did not already do this) : lsusb. In the output I obtain, I can see this line :

     Bus 002 Device 006: ID 15ba:002a Olimex Ltd.  ARM-USB-TINY-H   JTAG  interface

The interface script file I use is  "olimex-arm-usb-tiny-h.cfg". To obtain this file I downloaded the sources of the last version of  openocd. To do this :
 
       git  clone  git://git.code.sf.net/p/openocd/code openocd

With these sources, you have two files "olimex-arm-usb-tiny-h.cfg". They are located in two distinct directories:

        tcl/interface/ftdi/ olimex-arm-usb-tiny-h.cfg    => I use this file
        tcl/interface/ olimex-arm-usb-tiny-h.cfg

In the same time you can also display in your next message the verbatim copy of the script you use for your target (no matter if you have modify/customize the version I have given in my last message). it's just to test your file with my environment that is operational, and give you a status about the result (perhaps there is a typographical error in your file, hence my request about a verbatim copy of your file).

Kind regards,

Christophe

[vision]

Hi there,

@JohnS: u r right, i have to ignore eclipse and first do it like in middle ages, with candlelight :-)

@Christophe: tnx, i am 1 step further

This is the script i use (after interface configuration):

---------------------------------------------------------------------------------------------------
# a20-olinuxino-micro-4gb
#---------------------------------------------------------------------------
adapter_khz 14000
transport select jtag
reset_config srst_only srst_nogate

echo "Version 0.1"

set _CHIPNAME a20

# Main DAP
#---------------------------------------------------------------------------
set _DAP_TAPID 0x5ba00477

jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0xf -expected-id $_DAP_TAPID

set _TARGETNAME $_CHIPNAME.cpu.0
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap -coreid 0
set _TARGETNAME $_CHIPNAME.cpu.1
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap -coreid 1

init

target smp $_CHIPNAME.cpu.0 $_CHIPNAME.cpu.1

halt

$_CHIPNAME.cpu.0 configure -event gdb-attach {
   echo "gdb-attach"
   targets $_CHIPNAME.cpu.0
   halt
   targets $_CHIPNAME.cpu.1
   halt
}

---------------------------------------------------------------------------------------------------

The JTAG connection works after the sunxi bootloader has started a kernel in NAND (android ?). The starting is halted.

Afterwards i start gdb (arm-none-eabi-gdb). Some gdb commands (info registers, ... ) are working, but loading my .elf fails with message "Address translation failure".

Questions:
- how can JTAG be enabled at boot time (before starting a kernel) ?   
- what causes "Address translation failure" (mmu initialisation) ?

kind regards

[Christophe]

Hi Vision,


- Your script works fine in my environment

- When I bought my board, the NAND was loaded with Android (I think is the same for your board).

- "Address translation failure"

• When you encounter an error, the message can be retrieved in openocd sources. If you are lucky, you can pick up useful information from these files. In your case, the message is in a function whose name contents the words "mmu" , "translate" and "va". So, I think your intuition is good.
• I bought the JTAG debug adapter (perhaps two days after you) just to see the processor behavior in a particular sequence of  less than 10 assembler instructions. Now I saw the result, I have stopped using the JTAG debug adapter. I have a lot of readings to understand about the ARMv7 architecture before writing a little program (at system level) and use openocd in order to debug it (I give me about 6 months before reusing the adapter). So, consider that I am a newbie in this field. I am sure you known much more than me on this topic (openoocd).

how can JTAG be enabled at boot time (before starting a kernel) ?

• I don't know whether this feature is included in u-boot.
• As I never be able to start, or use openocd when only one core has been activated (I tried several setups in openocd scripts, except the good one, of course), I think you will have to activate the second core (and so, avoid all error messages that are displayed).

Kind regards