1.50 EUR DDR1 Memory now available!! How to replace HYNIX DDR?

[jlumme]

Hi jaycarlson,

Yes, I also got it to work with cas2.5 and with speed of 96MHz.
Or, well, I have 5 boards and 2 boot fine now. Strangely, I am still having memory recognition problems with some of those chips (they are recognized as size of 0 or 16MB).. Did you ever encounter this type of problem ?

[jlumme]

Just as a note for others possibly considering similar RAM chips. We are successfully now using both memories in our product.
The problems with RAM not being recognized well turned out to be soldering issues 

[srungerson]

Well... this is to the thread that will never die.

We made 3000 of the IMX23's since the thread started and now we have 20 that passed returned to us as field failures. In debug we see they now show DDR init errors... just like a bad memory... Since they passes once we looked further and see the boot is OK if the part is well warmer than room temp...

So now it's back to the dwg. board

We have tried to see if we can fine tune the MT46V32M16P-5B we are using. So far nothing has helped.

Questions:

CASLAT bit now = 2 (per Micron data sheet) ... could CASLAT_LIN or CASLAT_LIN_GATE (now 0x0404 or 2 cycles) be changed in any way to "fine tune".. We tried 0x0505.. and 0x0303 hoping a miracle would occur and this would dismiss any heat or other layout issues. So far ... it seems clear we cannot tinker with these bit mapped values.

So the big question.. IF we see a> theses few boards work when heated and b> 1000's of others work at all temps , is there ANY registers left to fine tune... or do just write the IMX and Memory combo on these boards as failed and discard them.. and ignore this scary discovery.

From a production perspective, fixing them is ALWAYS preferred so we do not get 100's more back someday due to giving up on this "clue" of a few heat related boards.

Any thoughts on other registers to fool with these boards or adjusting the ones above would be welcome!

thanks
-SR

[srbyers]

I don't know anything about DDR timing, etc., but with such a low failure rate & temperature related, maybe you should consider other things such as marginal regulator voltages or decoupling (noise) on the supply lines?

[JohnS]

What do the signals look like when failing cf working?

I hope you have good tools and talent...

John

[jlumme]

Though I'm not HW engineer, and temperature related failures seem HW design issues, from SW side you could try lowering the actual clock of the DDR.
You would need to play with emi divider and frac divider for this purpose - In uboot this is done in mxs_adjust_memory_clock of spl_mem_init.c. I'm sure very similar code is somewhere in bootlets as well.