ESP32 Ethernet hardware clock changed

[glmnet]

HI, I'm reviewing this board and I see you've removed the 50Mhz oscillator connected to GPIO0 around version C or D, and now are using ESP32 internal oscillator connected to GPIO17.
What really worries my is ESP IDF recommends this as test only, and I need something to be reliable. Why is this so?

This is where ESP-IDF do not recommend using internal APLL for PHY clock: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/kconfig.html#config-eth-rmii-clk-output-gpio0

[LubOlimex]

Which board exactly? You forgot to mention the name of the board.