why do DDR3 pins appear mixed in A64 schematic?

[ericsm]

Hello,
(not sure if it's the right section of the forum to post this topic, didn't find A64 section...)
I was looking at the A64 board schematic [1], and the DDR3 pin connections seem strange and mixed up to me.
For example, the SDQ0 pin on the CPU is connected to the SDQ1 pin on the memory chip (instead of SDQ0).
Does anyone know why the DDR3 pins are connected like this? (also checked the Pine64 schematic, and the pins seem also mixed but in a different order, but when I check in A20 schematics connection is normal...)

[1] https://github.com/OLIMEX/OLINUXINO/blob/master/HARDWARE/A64-OLinuXino/A64-OlinuXino_Rev_A.pdf

[Lurch]

I think this was answered, but I can't find the reference. Essentially, it doesn't matter if the pins are correct (0->0, 1->1 ...), the memory will store and retrieve the data. For that reason, developers are concentrating on using the easiest layout, not on an absolutely correct pin-number to pin-number connection.

[JohnS]

Yes it was asked & answered but maybe a different board.

It's absolutely standard practice and has been for at least 30 years that I know.

Think about it.  A bit is written to storage bit X.  Later the same bit is to be read.  Where X is does not matter so long as it is the same place.

John