Using SRAM on the iCE40HX1K-EVB with icestorm?

[michaelengel]

Hi,

I'm trying to use the SRAM chip on the iCE40HX1K-EVB board, but could not find any examples how to correctly set up Verilog inout ports required for connecting to the SRAM's data bus.

In my top module, I try to define the following:
module Top(
  input clk,
  output [17:0] sa, // SRAM address bus
  inout  [15:0] sd, // SRAM data bus
  output soe, // SRAM output enable
  output swe, // SRAM write enable
  output scs // SRAM chip select
);


When trying to synthesize this, I get the following error message:
fatal error: toplevel inout port 'sd[0]' not connected to SB_IO PACKAGE_PIN

One of the few examples I found using inout ports is https://github.com/cliffordwolf/icestorm/blob/master/icefuzz/tests/sb_gb_io.v.
This uses a SB_GB_IO construct. However, I can't seem to figure out how to correctly initialize this construct for my use case.

Any help and/or example code is appreciated.

-- Michael

Software versions used:
Yosys 0.7+     253 (git sha1 acd6cfa, clang 8.0.0 -fPIC -Os)
arachne-pnr 0.1+203+ 0 (git sha1 7e135ed, c++ 8.0.0 -O2)


The relevant bits from the pcf file:
set_io sd[0] 62
set_io sd[1] 63
set_io sd[2] 64
set_io sd[3] 65
set_io sd[4] 66
set_io sd[5] 68
set_io sd[6] 69
set_io sd[7] 71
set_io sd[8] 72
set_io sd[9] 60
set_io sd[10] 59
set_io sd[11] 57
set_io sd[12] 56
set_io sd[13] 54
set_io sd[14] 53
set_io sd[15] 52
set_io sa[0] 79
set_io sa[1] 80
set_io sa[2] 81
set_io sa[3] 82
set_io sa[4] 83
set_io sa[5] 85
set_io sa[6] 86
set_io sa[7] 87
set_io sa[8] 89
set_io sa[9] 90
set_io sa[10] 91
set_io sa[11] 93
set_io sa[12] 94
set_io sa[13] 95
set_io sa[14] 96
set_io sa[15] 97
set_io sa[16] 99
set_io sa[17] 100

set_io soe 74
set_io swe 73
set_io scs 78

[michaelengel]

A quick follow-up - I have adapted an SRAM test from the mystorm/blackICE board (which uses the next larger iCE40 FPGA, the iCE40HX4K) to run on the iCE40HX1K-EVB. The test simply writes an incrementing counter value to consecutive SRAM addresses, reads the value back and displays the two MSB (bits 14 and 15) on the board's LEDs (and outputs bits 8-13 to some of the pins of the I/O header). So far, it's looking good, I'm going to test a small CPU using the SRAM next.

Original project at github:
https://github.com/mattvenn/fpga-sram

Modified for the iCE40HX1K-EVB and yosys/icestorm:
http://multicores.org/sram.zip

-- Michael

[brmlst]

Hi Michael,
the link to your modified example for Olimex EVB is dead, can you make it available again?

Thanks

[michaelengel]

Hi,

thanks for the notice - you can find the code in my github repository now:
https://github.com/michaelengel/iCE40HX1K-EVB

Best, Michael