Disabling SPI FLASH and using SPI0, SPI1

[sporubcan]

Hi,
I use T2(A20) lime2. I would like to know, how to disable SPI FLASH in uBoot or where is it referenced. I need to have free SPI00 with both Chip Selects available.
Thank you very much!
Samuel

[LubOlimex]

Does your board have eMMC? Where are you booting from?

[sporubcan]

Yes, it has eMMC. I boot from SD card, but will use eMMC in the future.

[sporubcan]

Does your board have eMMC? Where are you booting from?

Yes, it has eMMC. I boot from SD card, but will use eMMC in the future.

[LubOlimex]

If you are going to use eMMC in fuutre, then avoid using SPI0 - all A20 boards with eMMC memory also come with SPI flash on SPI0 line. This flash is used to assist booting. This means that if you disable SPI0 by software means you still can't use it, since there would still be flash memory placed on the lines.

Also notice that SPI0 has only one CS, not two. In the documentation it is named "SPI0_CS0".

Why do you need exactly SPI0? Aren't SPI1 and SPI2 at each UEXT connector sufficient? Each has two CS pins.

Best regards,
Lub/OLIMEX

[sporubcan]

If you are going to use eMMC in fuutre, then avoid using SPI0 - all A20 boards with eMMC memory also come with SPI flash on SPI0 line. This flash is used to assist booting. This means that if you disable SPI0 by software means you still can't use it, since there would still be flash memory placed on the lines.

Also notice that SPI0 has only one CS, not two. In the documentation it is named "SPI0_CS0".

Why do you need exactly SPI0? Aren't SPI1 and SPI2 at each UEXT connector sufficient? Each has two CS pins.

Best regards,
Lub/OLIMEX

I have 4 SPI devices, so I need 4 Chip selects. I found SPI0_CS1 on pin PI4.

I tried to use SPI1, but I am unable to initialize SPI1_CS1 on PI15 (I see no SPIDEV for that chipselect in /dev). This is how I made device tree file:

Code Select Expand

/dts-v1/;
/plugin/;

/ {
compatible = "allwinner,sun7i-a20";

fragment@0 {
target-path = "/aliases";
__overlay__ {
spi1 = "/soc@1c00000/spi@1c06000";
};
};

fragment@1 {
target = <&spi1>;
__overlay__ {
status = "okay";
pinctrl-names = "default", "default", "default";
pinctrl-0 = <&spi1_pins_a>;
pinctrl-1 = <&spi1_cs0_pins_a>;
pinctrl-2 = <&spi1_cs1_pins_a>;
};
};

fragment@2 {
target = <&pio>;
__overlay__ {
spi1_pins_a: spi1@0 {
pins = "PI17", "PI18", "PI19";
function = "spi1";
drive = <0>;
pull = <0>;
};

spi1_cs0_pins_a: spi1_cs0@0 {
pins = "PI16";
function = "spi1";
drive = <0>;
pull = <0>;
};

spi1_cs1_pins_a: spi1_cs1@0 {
                                pins = "PI15";
                                function = "spi1";
                                drive = <0>;
                                pull = <0>;
                        };
};
};
};



I am also unable to find SPI2_CS1 in the schematic.

Currently I see only two spidevs: 1.0 and 2.0.

[LubOlimex]

SPI2_CS1 should be PB13, at GPIO-3 header.

What about SPI3? I am looking at this document:

http://dl.linux-sunxi.org/A20/A20%20User%20Manual%202013-03-22.pdf

[sporubcan]

SPI2_CS1 should be PB13, at GPIO-3 header.

What about SPI3? I am looking at this document:

http://dl.linux-sunxi.org/A20/A20%20User%20Manual%202013-03-22.pdf

Thank you, you're right. SPI1 and SPI2 have two chipselects too. But I am unable to activate CS1 in both cases. I made own device tree file, where I put manually GPIO pins on which these CS are mapped, but it doesn't work.

I will appreciate any help which will make SPI1_CS1 and SPI2_CS1 working.

[sporubcan]

SPI2_CS1 should be PB13, at GPIO-3 header.

What about SPI3? I am looking at this document:

http://dl.linux-sunxi.org/A20/A20%20User%20Manual%202013-03-22.pdf

SPI3 is unusable, there is Ethernet on that pins.